A Low Latency and Power ASIC Design of Modular Network Interfaces for Network on Chip

The implementation of a high-performance Network on Chip (NoC) requires an efficient design of the network interface (NI) unit that connects the switched network to the IP cores. However, different interfaces’ specification of integrated components and different flow control is used by NoC router raises a considerable difficulty for adopting NoC techniques. The architecture of NIs must be modular to allow IPs and interconnections to be designed independently from each other. The power of this NI should be small and its latency must be kept as low as possible. Previous studies show that the decrease of end to end latency between IPs cores can be done by reducing the latency of NoC components and decreasing the jitter between successive packets. In this paper, we present new modular NI architectures between IPs and router with low power and latency. Proposed NIs allows systematic design flow for accelerating the design cycle and hide implementation details of the network. The modular design is obtained through two separations between data flows and IP side and the network side. The low latency and jitter reduction between successive packets are obtained by a separation between header and payload memories. The low power is obtained through the implementation of these NIs using low power library with 130 nm technology. Experimental results show that the proposed NIs outperform conventionally architecture in terms of power and latency.